Modern system on a chip (SoCs) are integrated circuits constructed using a variety of modules and/or sub-systems designed to work together to perform a specific function. The systems and subsystems are integrated together using a communication medium such as a system bus. Often, different modules and systems have different timing requirements. The integration of modules with varying clock and timing requirements can cause challenges in the design, testing, and verification of complex SoCs.
One such challenge is the mitigation of metastability. Metastability, a state in which data is unstable due to a conflicting and infinite feedback loop within a circuit, can cause a variety of serious consequences. The unstable data can be fed to other loci in the design and can lead to dangerously high current flow and even circuit damage. Furthermore, different fan-out cones within the circuit path might read the unstable signal as different values, which may cause the design to enter into an unknown functional state, creating data bottlenecks and operational issues. Additionally, such a situation can create excessive propagation delay, leading to timing issues. Data loss and data incoherency can also have adverse effects on any computing system. These factors can cause disruptions in computation, erroneous results, or other device malfunctions.
Communication throughput and latency within a system both depend on the design of the module interfaces, including the transmit and receive clock rates and communication patterns based on typical operation of the modules. Due to the asynchronous nature of the sending and receiving circuitry, a simple mechanism for maintaining data synchronicity, such as a handshake protocol, is prone to problems that could lead to unreliable data transfer. Lost or garbled data can greatly reduce system functionality. Thus, data speed and data integrity are two important factors in any intercommunication scheme.
A communication interface between two processors or controllers typically involves bi-directional data transfer. For example, a processor/controller might interface to another processor to receive and transmit packets of data. The data transfers can be synchronous or asynchronous. A synchronous data transfer uses a mechanism such as a local or system clock to synchronize the speed of the transmitting and the receiving processors. Synchronous data transfer mode simplifies many design considerations within a system but cannot accommodate different clock speeds or processor operating frequencies—however, the ability to account for differing operational frequencies across a design has become a requirement in modern systems.
A large-scale architecture with many subsystems typically contains a large number and variety of interacting clock domains. Synchronizing all of the clock domains is often a prohibitive endeavor because of engineering costs, power consumption, and project-level risks. Accordingly, such architectures and designs increasingly utilize multiple asynchronous clock domains.
But, with the increasing inclusion of various operational frequencies within a design, designers of SoCs and other integrated circuits face challenges when confronted with the need to transfer data between multiple subsystems. Such data can include asynchronous data such as control and configuration commands, isochronous data such as video packets that have strict temporal and jitter requirements, and/or other synchronous, periodic data. Some applications require high levels of data integrity and/or bandwidth. In summary, systems and methods of data transfer between such entities are an invaluable part of modern logic circuit design.